Ascertaining the correct operation of digital logic circuits requires verification of functional behavior as well as correct operation at desired clock rates. Failures that cause logic to malfunction at desired clock rates are referred to as delay faults or as AC faults. These delay faults, particularly those occurring within integrated circuits, are typically due to random variations in process parameters that may cause device and/or wiring propagation delays to exceed specified limits. The detection of a delay fault normally requires the application of a two-pattern test: the first pattern applies an initialization value at the site of the suspected fault, and the second pattern provokes a logical transition at the site of the fault and propagates its effect to a primary output or latch. The two-pattern test will typically be structured to provoke a 0-to-1 transition at the site of the fault to test for a slow-to-rise (STR) fault, and will be structured to provoke a 1-to-0 transition to test for a slow-to-fall (STF) fault. By measuring the output of the circuit after a desired time interval it can be ascertained if a delay fault exists in the circuit.
As such, delay tests for logic circuits differ from static, stuck-at tests in that they characterize the dynamic properties of the circuit, such as the propagation delay. Two types of delay tests that are of most interest herein are the skewed-load test and the broad-side test.
Both of these delay tests employ a scan chain (by example, a scan chain based on a level sensitive scan design (LSSD)) for storing a logic initializing vector (Vl) and for applying V1 to a circuit under test. The application of V1 is followed by the application of a second vector (V2) that launches at least one transition through the circuit under test. These two vectors may be referred to collectively as a delay test pair. The output of the circuit under test is subsequently sampled to determine if the transition has propagated through the circuit within some specified maximum propagation time. The skewed-load test and the broad-side test differ from one another primarily in how the second vector V2 is generated.
In the skewed-load transition test the second vector V2 of the delay test pair is a one bit shift from the first vector V1 of the pair. This type of delay test is useful for, by example, testing a block of combinational logic that is interposed between two scan chains. The first scan chain is used to apply the vectors and the second scan chain is used to latch the circuit outputs. In the skewed-load test protocol, in order not to disturb the logic initialized by the first vector of the delay test pair, the second vector of the pair (the vector V2 that launches the transition) is required to be a next (i.e., one bit-shift) pattern in the scan chain.
Although a skewed-load transition test is attractive from a timing point of view, there are various problems that may arise during its use. A problem of most concern herein is the limited number of second vectors that can be generated because of the constraint imposed by the logic state(s) of the first vector. In this regard reference can be had to an article entitled "Scan-Based Transition Test", by Jacob Savir and Srinivas Patil, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 12, No. 8, August 1993, pp. 1232-1241.
By example, and referring to FIG. 1A, assume that a scan chain stores the following initializing vector: EQU 0 0 1 0,
and that the desired second vector is: EQU 1 0 0 1.
For this case shifting in a one bit (from the left) results in the generation of the desired second vector, as shown in FIG. 1B. However, if the desired second vector is instead: EQU 1 0 1 1,
then the desired second vector cannot be generated. This is because the third bit (from the left) of the second vector is constrained to be a zero by the second bit of the initializing vector being a zero. That is, because of the one bit shift the third bit must assume the logic state of the second bit.
The broad-side delay test is also a form of the scan-based delay test where, as shown in FIGS. 2A and 2B, the first vector pattern is scanned into the chain, and the second vector of the delay pair is supplied through one or more blocks of combinational logic being tested. Both the launching of the transition and the capture of the resulting circuit response are accurately timed according to the system requirements. Since the first vector is applied through the scan chain and the second vector from the logic being tested, the broad-side delay test can be viewed as a semi-functional test that is run at speed. This approach is different from the skewed-load transition test, where both the first and second vectors of the delay test pair are applied by the scan hardware.
However, in many cases the broad-side delay test coverage is relatively low. This is due primarily to the limited potential of the broad-side approach to apply a rich set of two-pattern tests. That is, the total number of second vector patterns is constrained to the number of different patterns that can be generated by the logic under test. In this regard reference may be had to a second article by J. Savir and S. Patil, "On broad-side delay test," Proc. 1994 VLSI Test Symposium, pp. 284-290, April, 1994, for a detailed discussion of the broad-side test.
Reference is also made to commonly-assigned U.S. Pat. No. 5,278,842, entitled "Delay Test Coverage Enhancement for Logic Circuitry Employing Level Sensitive Scan Design", which was issued on Jan. 11, 1994 to Robert W. Berry, Jr. and to the inventor of the subject matter of this patent application. This patent discloses one approach to overcoming the foregoing problems that relate to shift-dependencies, wherein a number of adjacent latches of a chain of shift register latches provide signals to different cones of logic. A `cone of logic` is considered to be associated with an output signal line of a logic circuit and those signal paths through which input signals influence the output signal.
The following commonly assigned U.S. Patents are all related to scan-based logic circuits and/or to the testing of logic circuits: U.S. Pat. No. 4,503,537, issued Mar. 5, 1985, entitled "Parallel Path Self-Testing System", to McAnney; U.S. Pat. No. 4,680,539, issued Jul. 14, 1987, entitled "General Linear Shift Register", to Tsai; U.S. Pat. No. 4,687,988, issued Aug. 18, 1987, entitled "Weighted Random Pattern Testing Apparatus And Method", to Eichelberger et al.; U.S. Pat. No. 4,688,223, issued Aug. 18, 1987, entitled "Weighted Random Pattern Testing Apparatus And Method", to Motika et al.; U.S. Pat. No. 4,698,830, issued Oct. 6, 1987, entitled "Shift Register Latch Arrangement For Enhanced Testability In Differential Cascode Voltage Switch Circuit", to Barzilai et al.; U.S. Pat. No. 4,745,355, issued May 17, 1988, entitled "Weighted Random Pattern Testing Apparatus And Method", to Eichelberger et al.; U.S. Pat. No. 4,801,870, issued Jan. 31, 1989, entitled "Weighted Random Pattern Testing Apparatus And Method", to Eichelberger et al.; U.S. Pat. No. 5,042,034, issued Aug. 20, 1991, entitled "By-Pass Boundary Scan Design" to Correale, Jr. et al.; and U.S. Pat. No. 5,150,366, issued Sep. 22, 1992, entitled "Reduced Delay Circuits For Shift Register Latch Scan Strings", to Bardell, Jr. et al.
The following two non-commonly assigned U.S. Patents are also of interest: U.S. Pat. No. 4,912,395, issued Mar. 27, 1990, entitled "Testable LSI Device Incorporating Latch/Shift Registers and Method of Testing Same", to Sato et al; and U.S. Pat. No. 5,130,988, issued Jul. 14, 1992, entitled "Software Verification by Fault Insertion", to Wilcox et al.